(1) Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to processes related to the formation of STI (shallow trench isolation).
(2) Background of the Invention and Description of Previous Art
The formation of integrated circuit devices on silicon substrates requires that a means be provided to electrically isolate the various circuit components such as MOSFETs (metal oxide silicon field effect transistors) from each other. To this end regions of field insulation, typically of silicon oxide, are formed adjacent to the circuit components. In the discussion as well as in the description of the embodiments of the invention, the words xe2x80x9coxidexe2x80x9d, xe2x80x9cnitridexe2x80x9d, and xe2x80x9coxynitridexe2x80x9d are frequently used for the sake of brevity and are always intended to refer to xe2x80x9csilicon oxidexe2x80x9d, xe2x80x9csilicon nitridexe2x80x9d, and xe2x80x9csilicon oxynitridexe2x80x9d respectively.
The well known method of local oxidation of silicon(LOCOS) to form field oxide isolation around semiconductive devices built into the surface of silicon wafers has been practiced for over twenty-five years and has served well to provide field isolation for many applications. Over the years many problems with LOCOS have surfaced which have been addressed in a great variety of ways. Most notable are the problems which deal with the growth of oxide under the hardmask used to define the oxide regions and the resultant uneven surface topology over the field oxide. The oxide penetration under the mask is commonly referred to as birds-beak. These problems still persist and become aggravated as the technology tends towards smaller, shallower devices at high densities.
A promising replacement for LOCOS field oxide isolation has been found in trench isolation. Although deep trench isolation(DTI) has been used nearly as long as LOCOS for bipolar transistor isolation, it has not been widely practiced in the manufacture of CMOS (complimentary metal oxide silicon) integrated circuits. More recently, however, as device densities increase and isolation widths become smaller, shallow trench isolation(STI) is gaining favor over LOCOS in CMOS technology. The Trenches are formed in the silicon around the semiconductor devices by reactive ion etching. A silicon nitride/pad oxide hardmask, similar to that used for LOCOS oxidation, is used to define the trenches. After etching, the trenches are first lined, preferably with a thin ( less than 200 xc3x85) layer of thermal silicon oxide and then filled, either with silicon oxide with another material such as polysilicon. The filler material is deposited conformally on the wafer by a CVD (chemical vapor deposition) process. The wafer is then planarized by CMP (chemical mechanical planarization) which removes excess filler from the surface.
In the process described herein, a thin layer (less than about 500 xc3x85 of silicon oxynitride is deposited onto the silicon oxide layer as an ARC (anti-reflective coating) in order to eliminate reflections from the subjacent silicon during the photolithographic patterning of the nitrideoxide hardmask. The presence of this ARC during planarization necessitates the use of a low oxide-to-nitride selectivity CMP process in order to properly remove it. Failure to completely remove the silicon oxynitride ARC will result in patches of silicon nitride remaining after the nitride etch. The low selectivity process, however, causes dishing over wide field regions. The dishing is ameliorated by removing filler material over non-field regions by wet etching through a reverse mask before CMP. If the oxynitride ARC could be easily removed before the filler material is deposited, a high oxide-to-nitride CMP process could be used. There would then be no dishing and consequently the need for the reverse mask and extra etching step would be eliminated. The present invention provides such a process.
Unlike LOCOS field isolation, the geometric features of STI are generally more abrupt, presenting sharp corners at both the top and bottom of the trenches. Sharp upper corners are particularly degrading and aggravate device performance issues which are stress related. In particular, major problems are encountered when STI is used in CMOS technology that are caused by electric field crowding at the edges of the active device regions. These problems include anomalous sub-threshold conduction and poor gate oxide integrity. In addition, tensile stresses are induced in the devices themselves by shrinkage of the trench filling oxide through densification of the oxide during subsequent annealing.
Koike, et.al., U.S. Pat. No. 5,578,518 shows a method for rounding the upper corners of silicon trenches whereby a thin 250 xc3x85 pad oxide under a polysilicon layer edge is recessed by undercutting with a wet etch prior to etching of the trench. The trench is then etched and a liner oxide is grown which rounds off the edge and simultaneously seals off the undercut. In a similar fashion, Moon, et.al., U.S. Pat. No. 5,719,085 recesses a 100 xc3x85 thick pad oxide under a silicon nitride layer edge. A first oxide is then grown which produces a birds beak under the nitride edges and rounds off the upper trench corners. The first oxide is removed and a second oxide is grown which extends the birds beak further under the nitride edge. Although the oxide stresses at the corners are diffused because of rounding, the nitride edge remains over the corners. Another application of an undercut pad oxide under an oxidation resistant layer edge is found in a recessed LOCOS isolation process cited by Vasquez, et.al., U.S. Pat. No. 5,455,194. Here undercutting of the pad oxide plays a role in suppressing lateral encroachment of oxide, also known as birds beak, in a poly buffered LOCOS process. A thin oxide, which does not fill the recess, is formed after the pad oxide is recessed. The recess is then filled with polysilicon which is subsequently oxidized.
It is an object of this invention to provide a method for improving the electrical characteristics of MOSFETs with channel regions defined and isolated by shallow trench isolation.
It is another object of this invention to provide a method for reducing upper corner stresses in shallow trench isolation regions.
It is yet another object of this invention to provide a method for forming a MOSFET isolated by STI with reduced mechanical stress, improved gate oxide integrity, and reduced electric field crowding at channel edges.
These objects are accomplished by plasma etching a silicon trench using a silicon nitridepad oxide hardmask with a silicon oxynitride ARC and then recessing the hardmask by wet chemical etching to expose the upper silicon corners of the silicon trench. A silicon oxide trench liner is then grown by a thermal oxidation process. Because the upper surfaces of the trench corners are exposed, the oxidation occurs both on top and on the sidewalls resulting in a rounding of the silicon corners. The silicon oxide trench liner is preferably formed by RTO (rapid thermal oxidation) using ISSG (in-situ steam generation).
It is yet another object of this invention to provide a method for forming a shallow trench lining oxide while simultaneously removing an anti-reflective coating.
It is yet another object of this invention to provide a method for forming a shallow trench lining oxide which permits the use of a high oxide selectivity process for planarizing shallow trench isolation.
It is still another process of this invention to provide a shallow trench lining process which eliminates the need for a reverse mask to prevent dishing of wide field regions during subsequent chemical mechanical planarization of shallow trench isolation.
These objects are accomplished by subjecting a freshly etched silicon trench by a first oxidation process whereby a major portion of a silicon oxynitride ARC is converted to silicon oxide while a sacrificial lining oxide is formed in the trench. The silicon oxynitride ARC is deposited onto the silicon nitride layer of the silicon nitridepad oxide hardmask and is used to eliminate light reflections during photolithographic patterning of the hardmask. The sacrificial oxide and the oxidized portion of the ARC is then removed by etching in aqueous HF. A final silicon oxide trench liner of a prescribed thickness is then formed by a second oxidation which also converts the remaining silicon oxynitride ARC to silicon oxide. The oxide lined trench is next filled with a filler material such as CVD silicon oxide. The wafer surface is then planarized into the silicon nitride layer by a high oxide-to-nitride selectivity CMP process, for example one which employs a polishing slurry containing CeO2.
It is yet another object of this invention to describe a process which combines both corner rounding of upper trench corners and the removal of a silicon oxynitride ARC prior to trench filling thereby eliminating the need of a reverse mask and the accompanying etch step while at the same time reducing mechanical stress, improving gate oxide integrity, and reducing electric field crowding at channel edges.
These objects are accomplished by plasma etching a silicon trench using a silicon nitridepad oxide hardmask with a silicon oxynitride ARC and then recessing the hardmask by wet chemical etching to expose the upper silicon corners of the silicon trench. Next a sacrificial oxide is grown, in a first oxidation step, whereby a portion of the silicon oxynitride ARC is converted to silicon oxide. The sacrificial oxide and the oxide over the ARC is then removed by wet chemical etching and a silicon oxide trench liner is grown by a second thermal oxidation step while the remaining oxynitride is converted to silicon oxide. The sacrificial oxide growth not only converts most of the ARC to oxide but also further improves the rounding of the upper trench corners. The sacrificial oxide and the lining oxide are preferably formed by RTO (rapid thermal oxidation) using ISSG (in-situ steam generation). The oxide lined trench is filled with a filler material such as CVD silicon oxide. The wafer surface is then planarized into the silicon nitride layer by a high oxide-to-nitride selectivity CMP process, for example one which employs a polishing slurry containing CeO2. An oxide-to-nitride selectivity of greater than about 10:1 is preferred.